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ATmega128
Table 104. Boundary-scan Signals for the ADC (Continued)
Direction
as Seen
Recommended
Input
Output Values when
Recommended Inputs
Signal
from the
when not
are Used, and CPU is
Name
MUXEN_7
MUXEN_6
MUXEN_5
MUXEN_4
MUXEN_3
MUXEN_2
MUXEN_1
MUXEN_0
NEGSEL_2
ADC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Input Mux bit 7
Input Mux bit 6
Input Mux bit 5
Input Mux bit 4
Input Mux bit 3
Input Mux bit 2
Input Mux bit 1
Input Mux bit 0
Input Mux for negative
in Use
0
0
0
0
0
0
0
1
0
not Using the ADC
0
0
0
0
0
0
0
1
0
input for differential signal,
bit 2
NEGSEL_1
Input
Input Mux for negative
0
0
input for differential signal,
bit 1
NEGSEL_0
Input
Input Mux for negative
0
0
input for differential signal,
bit 0
PASSEN
Input
Enable pass-gate of gain
1
1
stages.
PRECH
Input
Precharge output latch of
1
1
comparator. (Active low)
SCTEST
Input
Switch-cap TEST enable.
0
0
Output from x10 gain
stage send out to Port Pin
having ADC_4
ST
Input
Output of gain stages will
0
0
settle faster if this signal is
high first two ACLK
periods after AMPEN goes
high.
VCCREN
Input
Selects Vcc as the ACC
0 0
reference voltage.
Note:
Incorrect setting of the switches in Figure 131 will make signal contention and may damage the
part. There are several input choices to the S&H circuitry on the negative input of the output com-
parator in Figure 131 . Make sure only one path is selected from either one ADC pin, Bandgap
reference source, or Ground.
If the ADC is not to be used during scan, the recommended input values from Table 104 should
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
Cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
263
2467X–AVR–06/11
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